agileRTOS (zrtos)  Version 0.8.0 (ghostbuster)
lib/w5500.h
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1 /*
2  * Copyright (c) 2024 ykat UG (haftungsbeschraenkt) - All Rights Reserved
3  *
4  * Permission for non-commercial use is hereby granted,
5  * free of charge, without warranty of any kind.
6  */
7 #ifndef ZRTOS_VFS_MODULE_W5500_DEFINITIONS__H
8 #define ZRTOS_VFS_MODULE_W5500_DEFINITIONS__H
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 #if 0
14 https://github.com/Wiznet/ioLibrary_Driver/tree/master/Ethernet
15 
16 //*****************************************************************************
17 //
18 //! \file w5500.h
19 //! \brief W5500 HAL Header File.
20 //! \version 1.0.0
21 //! \date 2013/10/21
22 //! \par Revision history
23 //! <2015/02/05> Notice
24 //! The version history is not updated after this point.
25 //! Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary.
26 //! >> https://github.com/Wiznet/ioLibrary_Driver
27 //! <2013/10/21> 1st Release
28 //! \author MidnightCow
29 //! \copyright
30 //!
31 //! Copyright (c) 2013, WIZnet Co., LTD.
32 //! All rights reserved.
33 //!
34 //! Redistribution and use in source and binary forms, with or without
35 //! modification, are permitted provided that the following conditions
36 //! are met:
37 //!
38 //! * Redistributions of source code must retain the above copyright
39 //! notice, this list of conditions and the following disclaimer.
40 //! * Redistributions in binary form must reproduce the above copyright
41 //! notice, this list of conditions and the following disclaimer in the
42 //! documentation and/or other materials provided with the distribution.
43 //! * Neither the name of the <ORGANIZATION> nor the names of its
44 //! contributors may be used to endorse or promote products derived
45 //! from this software without specific prior written permission.
46 //!
47 //! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
48 //! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
49 //! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50 //! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
51 //! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
52 //! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
53 //! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
54 //! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
55 //! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
56 //! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
57 //! THE POSSIBILITY OF SUCH DAMAGE.
58 //
59 //*****************************************************************************
60 
61 //
62 
63 
64 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
65 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
66 
67 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
68 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
69 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
70 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
71 
72 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
73 
74 //////////////////////////////
75 //-------------------------- defgroup ---------------------------------
76 /**
77  * @defgroup W5500 W5500
78  *
79  * @brief WHIZCHIP register defines and I/O functions of @b W5500.
80  *
81  * - @ref WIZCHIP_register : @ref Common_register_group and @ref Socket_register_group
82  * - @ref WIZCHIP_IO_Functions : @ref Basic_IO_function, @ref Common_register_access_function and @ref Socket_register_access_function
83  */
84 
85 
86 /**
87  * @defgroup WIZCHIP_register WIZCHIP register
88  * @ingroup W5500
89  *
90  * @brief WHIZCHIP register defines register group of @b W5500.
91  *
92  * - @ref Common_register_group : Common register group
93  * - @ref Socket_register_group : \c SOCKET n register group
94  */
95 
96 
97 /**
98  * @defgroup WIZCHIP_IO_Functions WIZCHIP I/O functions
99  * @ingroup W5500
100  *
101  * @brief This supports the basic I/O functions for @ref WIZCHIP_register.
102  *
103  * - <b> Basic I/O function </b> \n
104  * WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() \n\n
105  *
106  * - @ref Common_register_group <b>access functions</b> \n
107  * -# @b Mode \n
108  * getMR(), setMR()
109  * -# @b Interrupt \n
110  * getIR(), setIR(), getIMR(), setIMR(), getSIR(), setSIR(), getSIMR(), setSIMR(), getINTLEVEL(), setINTLEVEL()
111  * -# <b> Network Information </b> \n
112  * getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR()
113  * -# @b Retransmission \n
114  * getRCR(), setRCR(), getRTR(), setRTR()
115  * -# @b PPPoE \n
116  * getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC(), getPSID(), setPSID(), getPHAR(), setPHAR(), getPMRU(), setPMRU()
117  * -# <b> ICMP packet </b>\n
118  * getUIPR(), getUPORTR()
119  * -# @b etc. \n
120  * getPHYCFGR(), setPHYCFGR(), getVERSIONR() \n\n
121  *
122  * - \ref Socket_register_group <b>access functions</b> \n
123  * -# <b> SOCKET control</b> \n
124  * getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IMR(), setSn_IMR(), getSn_IR(), setSn_IR()
125  * -# <b> SOCKET information</b> \n
126  * getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT()
127  * getSn_MSSR(), setSn_MSSR()
128  * -# <b> SOCKET communication </b> \n
129  * getSn_RXBUF_SIZE(), setSn_RXBUF_SIZE(), getSn_TXBUF_SIZE(), setSn_TXBUF_SIZE() \n
130  * getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR() \n
131  * getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR() \n
132  * getSn_TX_FSR(), getSn_RX_RSR(), getSn_KPALVTR(), setSn_KPALVTR()
133  * -# <b> IP header field </b> \n
134  * getSn_FRAG(), setSn_FRAG(), getSn_TOS(), setSn_TOS() \n
135  * getSn_TTL(), setSn_TTL()
136  */
137 
138 
139 
140 /**
141  * @defgroup Common_register_group Common register
142  * @ingroup WIZCHIP_register
143  *
144  * @brief Common register group\n
145  * It set the basic for the networking\n
146  * It set the configuration such as interrupt, network information, ICMP, etc.
147  * @details
148  * @sa MR : Mode register.
149  * @sa GAR, SUBR, SHAR, SIPR
150  * @sa INTLEVEL, IR, IMR, SIR, SIMR : Interrupt.
151  * @sa _RTR_, _RCR_ : Data retransmission.
152  * @sa PTIMER, PMAGIC, PHAR, PSID, PMRU : PPPoE.
153  * @sa UIPR, UPORTR : ICMP message.
154  * @sa PHYCFGR, VERSIONR : etc.
155  */
156 
157 
158 
159 /**
160  * @defgroup Socket_register_group Socket register
161  * @ingroup WIZCHIP_register
162  *
163  * @brief Socket register group.\n
164  * Socket register configures and control SOCKETn which is necessary to data communication.
165  * @details
166  * @sa Sn_MR, Sn_CR, Sn_IR, Sn_IMR : SOCKETn Control
167  * @sa Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information
168  * @sa Sn_MSSR, Sn_TOS, Sn_TTL, Sn_KPALVTR, Sn_FRAG : Internet protocol.
169  * @sa Sn_RXBUF_SIZE, Sn_TXBUF_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication
170  */
171 
172 
173 
174  /**
175  * @defgroup Basic_IO_function Basic I/O function
176  * @ingroup WIZCHIP_IO_Functions
177  * @brief These are basic input/output functions to read values from register or write values to register.
178  */
179 
180 /**
181  * @defgroup Common_register_access_function Common register access functions
182  * @ingroup WIZCHIP_IO_Functions
183  * @brief These are functions to access <b>common registers</b>.
184  */
185 
186 /**
187  * @defgroup Socket_register_access_function Socket register access functions
188  * @ingroup WIZCHIP_IO_Functions
189  * @brief These are functions to access <b>socket registers</b>.
190  */
191  #endif
192 //------------------------------- defgroup end --------------------------------------------
193 //----------------------------- W5500 Common Registers IOMAP -----------------------------
194 typedef enum{
195  /**
196  * @ingroup Common_register_group
197  * @brief Mode Register address(R/W)\n
198  * @ref MR is used for S/W reset, ping block mode, PPPoE mode and etc.
199  * @details Each bit of @ref MR defined as follows.
200  * <table>
201  * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
202  * <tr> <td>RST</td> <td>Reserved</td> <td>WOL</td> <td>PB</td> <td>PPPoE</td> <td>Reserved</td> <td>FARP</td> <td>Reserved</td> </tr>
203  * </table>
204  * - \ref MR_RST : Reset
205  * - \ref MR_WOL : Wake on LAN
206  * - \ref MR_PB : Ping block
207  * - \ref MR_PPPOE : PPPoE mode
208  * - \ref MR_FARP : Force ARP mode
209  */
210  ZRTOS_VFS_MODULE_W5500_REGISTER__MR = 0x0000
211 
212  /**
213  * @ingroup Common_register_group
214  * @brief Gateway IP Register address(R/W)
215  * @details @ref GAR configures the default gateway address.
216  */
217  ,ZRTOS_VFS_MODULE_W5500_REGISTER__GAR = 0x0001
218 
219  /**
220  * @ingroup Common_register_group
221  * @brief Subnet mask Register address(R/W)
222  * @details @ref SUBR configures the subnet mask address.
223  */
224  ,ZRTOS_VFS_MODULE_W5500_REGISTER__SUBR = 0x0005
225 
226  /**
227  * @ingroup Common_register_group
228  * @brief Source MAC Register address(R/W)
229  * @details @ref SHAR configures the source hardware address.
230  */
231  ,ZRTOS_VFS_MODULE_W5500_REGISTER__SHAR = 0x0009
232 
233  /**
234  * @ingroup Common_register_group
235  * @brief Source IP Register address(R/W)
236  * @details @ref SIPR configures the source IP address.
237  */
238  ,ZRTOS_VFS_MODULE_W5500_REGISTER__SIPR = 0x000F
239 
240  /**
241  * @ingroup Common_register_group
242  * @brief Set Interrupt low level timer register address(R/W)
243  * @details @ref INTLEVEL configures the Interrupt Assert Time.
244  */
245  ,ZRTOS_VFS_MODULE_W5500_REGISTER__INTLEVEL = 0x0013
246 
247  /**
248  * @ingroup Common_register_group
249  * @brief Interrupt Register(R/W)
250  * @details @ref IR indicates the interrupt status. Each bit of @ref IR will be still until the bit will be written to by the host.
251  * If @ref IR is not equal to x00 INTn PIN is asserted to low until it is x00\n\n
252  * Each bit of @ref IR defined as follows.
253  * <table>
254  * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
255  * <tr> <td>CONFLICT</td> <td>UNREACH</td> <td>PPPoE</td> <td>MP</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr>
256  * </table>
257  * - \ref IR_CONFLICT : IP conflict
258  * - \ref IR_UNREACH : Destination unreachable
259  * - \ref IR_PPPoE : PPPoE connection close
260  * - \ref IR_MP : Magic packet
261  */
262  ,ZRTOS_VFS_MODULE_W5500_REGISTER__IR = 0x0015
263 
264  /**
265  * @ingroup Common_register_group
266  * @brief Interrupt mask register(R/W)
267  * @details @ref _IMR_ is used to mask interrupts. Each bit of @ref _IMR_ corresponds to each bit of @ref IR.
268  * When a bit of @ref _IMR_ is and the corresponding bit of @ref IR is an interrupt will be issued. In other words,
269  * if a bit of @ref _IMR_ is an interrupt will not be issued even if the corresponding bit of @ref IR is \n\n
270  * Each bit of @ref _IMR_ defined as the following.
271  * <table>
272  * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
273  * <tr> <td>IM_IR7</td> <td>IM_IR6</td> <td>IM_IR5</td> <td>IM_IR4</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr>
274  * </table>
275  * - \ref IM_IR7 : IP Conflict Interrupt Mask
276  * - \ref IM_IR6 : Destination unreachable Interrupt Mask
277  * - \ref IM_IR5 : PPPoE Close Interrupt Mask
278  * - \ref IM_IR4 : Magic Packet Interrupt Mask
279  */
280  //M20150401 : Rename SYMBOE ( Re-define error in a compile)
281  //,ZRTOS_VFS_MODULE_W5500_REGISTER__IMR = 0x0016
282  ,ZRTOS_VFS_MODULE_W5500_REGISTER___IMR_ = 0x0016
283 
284  /**
285  * @ingroup Common_register_group
286  * @brief Socket Interrupt Register(R/W)
287  * @details @ref SIR indicates the interrupt status of Socket.\n
288  * Each bit of @ref SIR be still until @ref Sn_IR is cleared by the host.\n
289  * If @ref Sn_IR is not equal to x00 the n-th bit of @ref SIR is and INTn PIN is asserted until @ref SIR is x00 */
290  ,ZRTOS_VFS_MODULE_W5500_REGISTER__SIR = 0x0017
291 
292  /**
293  * @ingroup Common_register_group
294  * @brief Socket Interrupt Mask Register(R/W)
295  * @details Each bit of @ref SIMR corresponds to each bit of @ref SIR.
296  * When a bit of @ref SIMR is and the corresponding bit of @ref SIR is Interrupt will be issued.
297  * In other words, if a bit of @ref SIMR is an interrupt will be not issued even if the corresponding bit of @ref SIR is
298  */
299  ,ZRTOS_VFS_MODULE_W5500_REGISTER__SIMR = 0x0018
300 
301  /**
302  * @ingroup Common_register_group
303  * @brief Timeout register address( 1 is 100us )(R/W)
304  * @details @ref _RTR_ configures the retransmission timeout period. The unit of timeout period is 100us and the default of @ref _RTR_ is x07D0.
305  * And so the default timeout period is 200ms(100us X 2000). During the time configured by @ref _RTR_, W5500 waits for the peer response
306  * to the packet that is transmitted by \ref Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command).
307  * If the peer does not respond within the @ref _RTR_ time, W5500 retransmits the packet or issues timeout.
308  */
309  //M20150401 : Rename SYMBOE ( Re-define error in a compile)
310  //,ZRTOS_VFS_MODULE_W5500_REGISTER__RTR = 0x0019
311  ,ZRTOS_VFS_MODULE_W5500_REGISTER___RTR_ = 0x0019
312 
313  /**
314  * @ingroup Common_register_group
315  * @brief Retry count register(R/W)
316  * @details @ref _RCR_ configures the number of time of retransmission.
317  * When retransmission occurs as many as ref _RCR_+1 Timeout interrupt is issued (@ref Sn_IR_TIMEOUT = '1').
318  */
319  //M20150401 : Rename SYMBOE ( Re-define error in a compile)
320  //,ZRTOS_VFS_MODULE_W5500_REGISTER__RCR = 0x001B
321  ,ZRTOS_VFS_MODULE_W5500_REGISTER___RCR_ = 0x001B
322 
323  /**
324  * @ingroup Common_register_group
325  * @brief PPP LCP Request Timer register in PPPoE mode(R/W)
326  * @details @ref PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.
327  */
328  ,ZRTOS_VFS_MODULE_W5500_REGISTER__PTIMER = 0x001C
329 
330  /**
331  * @ingroup Common_register_group
332  * @brief PPP LCP Magic number register in PPPoE mode(R/W)
333  * @details @ref PMAGIC configures the 4bytes magic number to be used in LCP negotiation.
334  */
335  ,ZRTOS_VFS_MODULE_W5500_REGISTER__PMAGIC = 0x001D
336 
337  /**
338  * @ingroup Common_register_group
339  * @brief PPP Destination MAC Register address(R/W)
340  * @details @ref PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process.
341  */
342  ,ZRTOS_VFS_MODULE_W5500_REGISTER__PHAR = 0x001E
343 
344  /**
345  * @ingroup Common_register_group
346  * @brief PPP Session Identification Register(R/W)
347  * @details @ref PSID configures the PPPoE sever session ID acquired during PPPoE connection process.
348  */
349  ,ZRTOS_VFS_MODULE_W5500_REGISTER__PSID = 0x0024
350 
351  /**
352  * @ingroup Common_register_group
353  * @brief PPP Maximum Segment Size(MSS) register(R/W)
354  * @details @ref PMRU configures the maximum receive unit of PPPoE.
355  */
356  ,ZRTOS_VFS_MODULE_W5500_REGISTER__PMRU = 0x0026
357 
358  /**
359  * @ingroup Common_register_group
360  * @brief Unreachable IP register address in UDP mode(R)
361  * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number
362  * which socket is not open and @ref IR_UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR indicates
363  * the destination IP address & port number respectively.
364  */
365  ,ZRTOS_VFS_MODULE_W5500_REGISTER__UIPR = 0x0028
366 
367  /**
368  * @ingroup Common_register_group
369  * @brief Unreachable Port register address in UDP mode(R)
370  * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number
371  * which socket is not open and @ref IR_UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR
372  * indicates the destination IP address & port number respectively.
373  */
374  ,ZRTOS_VFS_MODULE_W5500_REGISTER__UPORTR = 0x002C
375 
376  /**
377  * @ingroup Common_register_group
378  * @brief PHY Status Register(R/W)
379  * @details @ref PHYCFGR configures PHY operation mode and resets PHY. In addition, @ref PHYCFGR indicates the status of PHY such as duplex, Speed, Link.
380  */
381  ,ZRTOS_VFS_MODULE_W5500_REGISTER__PHYCFGR = 0x002E
382 
383  // Reserved = 0x002F
384  // Reserved = 0x0030
385  // Reserved = 0x0031
386  // Reserved = 0x0032
387  // Reserved = 0x0033
388  // Reserved = 0x0034
389  // Reserved = 0x0035
390  // Reserved = 0x0036
391  // Reserved = 0x0037
392  // Reserved = 0x0038
393 
394  /**
395  * @ingroup Common_register_group
396  * @brief chip version register address(R)
397  * @details @ref VERSIONR always indicates the W5500 version as @b 0x04.
398  */
399  ,ZRTOS_VFS_MODULE_W5500_REGISTER__VERSIONR = 0x0039
400 
401 }zrtos_vfs_module_w5500_register_t;
402 
403 //----------------------------- W5500 Socket Registers IOMAP -----------------------------
404 typedef enum{
405  /**
406  * @ingroup Socket_register_group
407  * @brief socket Mode register(R/W)
408  * @details @ref Sn_MR configures the option or protocol type of Socket n.\n\n
409  * Each bit of @ref Sn_MR defined as the following.
410  * <table>
411  * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
412  * <tr> <td>MULTI/MFEN</td> <td>BCASTB</td> <td>ND/MC/MMB</td> <td>UCASTB/MIP6B</td> <td>Protocol[3]</td> <td>Protocol[2]</td> <td>Protocol[1]</td> <td>Protocol[0]</td> </tr>
413  * </table>
414  * - @ref Sn_MR_MULTI : Support UDP Multicasting
415  * - @ref Sn_MR_BCASTB : Broadcast block <b>in UDP Multicasting</b>
416  * - @ref Sn_MR_ND : No Delayed Ack(TCP) flag
417  * - @ref Sn_MR_MC : IGMP version used <b>in UDP mulitcasting</b>
418  * - @ref Sn_MR_MMB : Multicast Blocking <b>in @ref Sn_MR_MACRAW mode</b>
419  * - @ref Sn_MR_UCASTB : Unicast Block <b>in UDP Multicating</b>
420  * - @ref Sn_MR_MIP6B : IPv6 packet Blocking <b>in @ref Sn_MR_MACRAW mode</b>
421  * - <b>Protocol</b>
422  * <table>
423  * <tr> <td><b>Protocol[3]</b></td> <td><b>Protocol[2]</b></td> <td><b>Protocol[1]</b></td> <td><b>Protocol[0]</b></td> <td>@b Meaning</td> </tr>
424  * <tr> <td>0</td> <td>0</td> <td>0</td> <td>0</td> <td>Closed</td> </tr>
425  * <tr> <td>0</td> <td>0</td> <td>0</td> <td>1</td> <td>TCP</td> </tr>
426  * <tr> <td>0</td> <td>0</td> <td>1</td> <td>0</td> <td>UDP</td> </tr>
427  * <tr> <td>0</td> <td>1</td> <td>0</td> <td>0</td> <td>MACRAW</td> </tr>
428  * </table>
429  * - @ref Sn_MR_MACRAW : MAC LAYER RAW SOCK \n
430  * - @ref Sn_MR_UDP : UDP
431  * - @ref Sn_MR_TCP : TCP
432  * - @ref Sn_MR_CLOSE : Unused socket
433  * @note MACRAW mode should be only used in Socket 0.
434  */
435  ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__MR = 0x0000
436 
437  /**
438  * @ingroup Socket_register_group
439  * @brief Socket command register(R/W)
440  * @details This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE.\n
441  * After W5500 accepts the command, the @ref Sn_CR register is automatically cleared to 0x00.
442  * Even though @ref Sn_CR is cleared to 0x00, the command is still being processed.\n
443  * To check whether the command is completed or not, please check the @ref Sn_IR or @ref Sn_SR.
444  * - @ref Sn_CR_OPEN : Initialize or open socket.
445  * - @ref Sn_CR_LISTEN : Wait connection request in TCP mode(<b>Server mode</b>)
446  * - @ref Sn_CR_CONNECT : Send connection request in TCP mode(<b>Client mode</b>)
447  * - @ref Sn_CR_DISCON : Send closing request in TCP mode.
448  * - @ref Sn_CR_CLOSE : Close socket.
449  * - @ref Sn_CR_SEND : Update TX buffer pointer and send data.
450  * - @ref Sn_CR_SEND_MAC : Send data with MAC address, so without ARP process.
451  * - @ref Sn_CR_SEND_KEEP : Send keep alive message.
452  * - @ref Sn_CR_RECV : Update RX buffer pointer and receive data.
453  */
454  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__CR = 0x0001
455 
456  /**
457  * @ingroup Socket_register_group
458  * @brief Socket interrupt register(R)
459  * @details @ref Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).\n
460  * When an interrupt occurs and the corresponding bit of @ref Sn_IMR is the corresponding bit of @ref Sn_IR becomes \n
461  * In order to clear the @ref Sn_IR bit, the host should write the bit to \n
462  * <table>
463  * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
464  * <tr> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>SEND_OK</td> <td>TIMEOUT</td> <td>RECV</td> <td>DISCON</td> <td>CON</td> </tr>
465  * </table>
466  * - \ref Sn_IR_SENDOK : <b>SEND_OK Interrupt</b>
467  * - \ref Sn_IR_TIMEOUT : <b>TIMEOUT Interrupt</b>
468  * - \ref Sn_IR_RECV : <b>RECV Interrupt</b>
469  * - \ref Sn_IR_DISCON : <b>DISCON Interrupt</b>
470  * - \ref Sn_IR_CON : <b>CON Interrupt</b>
471  */
472  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__IR = 0x0002
473 
474  /**
475  * @ingroup Socket_register_group
476  * @brief Socket status register(R)
477  * @details @ref Sn_SR indicates the status of Socket n.\n
478  * The status of Socket n is changed by @ref Sn_CR or some special control packet as SYN, FIN packet in TCP.
479  * @par Normal status
480  * - @ref SOCK_CLOSED : Closed
481  * - @ref SOCK_INIT : Initiate state
482  * - @ref SOCK_LISTEN : Listen state
483  * - @ref SOCK_ESTABLISHED : Success to connect
484  * - @ref SOCK_CLOSE_WAIT : Closing state
485  * - @ref SOCK_UDP : UDP socket
486  * - @ref SOCK_MACRAW : MAC raw mode socket
487  *@par Temporary status during changing the status of Socket n.
488  * - @ref SOCK_SYNSENT : This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
489  * - @ref SOCK_SYNRECV : It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
490  * - @ref SOCK_FIN_WAIT : Connection state
491  * - @ref SOCK_CLOSING : Closing state
492  * - @ref SOCK_TIME_WAIT : Closing state
493  * - @ref SOCK_LAST_ACK : Closing state
494  */
495  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__SR = 0x0003
496 
497  /**
498  * @ingroup Socket_register_group
499  * @brief source port register(R/W)
500  * @details @ref Sn_PORT configures the source port number of Socket n.
501  * It is valid when Socket n is used in TCP/UDP mode. It should be set before OPEN command is ordered.
502  */
503  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__PORT = 0x0004
504 
505  /**
506  * @ingroup Socket_register_group
507  * @brief Peer MAC register address(R/W)
508  * @details @ref Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or
509  * it indicates that it is acquired in ARP-process by CONNECT/SEND command.
510  */
511  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__DHAR = 0x0006
512 
513  /**
514  * @ingroup Socket_register_group
515  * @brief Peer IP register address(R/W)
516  * @details @ref Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket n is used in TCP/UDP mode.
517  * In TCP client mode, it configures an IP address of TCP serverbefore CONNECT command.
518  * In TCP server mode, it indicates an IP address of TCP clientafter successfully establishing connection.
519  * In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command.
520  */
521  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__DIPR = 0x000C
522 
523  /**
524  * @ingroup Socket_register_group
525  * @brief Peer port register address(R/W)
526  * @details @ref Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when Socket n is used in TCP/UDP mode.
527  * In TCP clientmode, it configures the listen port number of TCP serverbefore CONNECT command.
528  * In TCP Servermode, it indicates the port number of TCP client after successfully establishing connection.
529  * In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command.
530  */
531  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__DPORT = 0x0010
532 
533  /**
534  * @ingroup Socket_register_group
535  * @brief Maximum Segment Size(Sn_MSSR0) register address(R/W)
536  * @details @ref Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n.
537  */
538  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__MSSR = 0x0012
539 
540  // Reserved 0x0014
541 
542  /**
543  * @ingroup Socket_register_group
544  * @brief IP Type of Service(TOS) Register(R/W)
545  * @details @ref Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n.
546  * It is set before OPEN command.
547  */
548  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__TOS = 0x0015
549  /**
550  * @ingroup Socket_register_group
551  * @brief IP Time to live(TTL) Register(R/W)
552  * @details @ref Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n.
553  * It is set before OPEN command.
554  */
555  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__TTL = 0x0016
556  // Reserved 0x0017
557  // Reserved 0x0018
558  // Reserved 0x0019
559  // Reserved 0x001A
560  // Reserved 0x001B
561  // Reserved 0x001C
562  // Reserved 0x001D
563 
564  /**
565  * @ingroup Socket_register_group
566  * @brief Receive memory size register(R/W)
567  * @details @ref Sn_RXBUF_SIZE configures the RX buffer block size of Socket n.
568  * Socket n RX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes.
569  * If a different size is configured, the data cannot be normally received from a peer.
570  * Although Socket n RX Buffer Block size is initially configured to 2Kbytes,
571  * user can re-configure its size using @ref Sn_RXBUF_SIZE. The total sum of @ref Sn_RXBUF_SIZE can not be exceed 16Kbytes.
572  * When exceeded, the data reception error is occurred.
573  */
574  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__RXBUF_SIZE = 0x001E
575 
576  /**
577  * @ingroup Socket_register_group
578  * @brief Transmit memory size register(R/W)
579  * @details @ref Sn_TXBUF_SIZE configures the TX buffer block size of Socket n. Socket n TX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes.
580  * If a different size is configured, the data can�t be normally transmitted to a peer.
581  * Although Socket n TX Buffer Block size is initially configured to 2Kbytes,
582  * user can be re-configure its size using @ref Sn_TXBUF_SIZE. The total sum of @ref Sn_TXBUF_SIZE can not be exceed 16Kbytes.
583  * When exceeded, the data transmission error is occurred.
584  */
585  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__TXBUF_SIZE = 0x001F
586 
587  /**
588  * @ingroup Socket_register_group
589  * @brief Transmit free memory size register(R)
590  * @details @ref Sn_TX_FSR indicates the free size of Socket n TX Buffer Block. It is initialized to the configured size by @ref Sn_TXBUF_SIZE.
591  * Data bigger than @ref Sn_TX_FSR should not be saved in the Socket n TX Buffer because the bigger data overwrites the previous saved data not yet sent.
592  * Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size,
593  * transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size,
594  * transmit the data after dividing into the checked size and saving in the Socket n TX buffer.
595  */
596  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__TX_FSR = 0x0020
597 
598  /**
599  * @ingroup Socket_register_group
600  * @brief Transmit memory read pointer register address(R)
601  * @details @ref Sn_TX_RD is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP.
602  * After its initialization, it is auto-increased by SEND command.
603  * SEND command transmits the saved data from the current @ref Sn_TX_RD to the @ref Sn_TX_WR in the Socket n TX Buffer.
604  * After transmitting the saved data, the SEND command increases the @ref Sn_TX_RD as same as the @ref Sn_TX_WR.
605  * If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs),
606  * then the carry bit is ignored and will automatically update with the lower 16bits value.
607  */
608  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__TX_RD = 0x0022
609 
610  /**
611  * @ingroup Socket_register_group
612  * @brief Transmit memory write pointer register address(R/W)
613  * @details @ref Sn_TX_WR is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP.\n
614  * It should be read or be updated like as follows.\n
615  * 1. Read the starting address for saving the transmitting data.\n
616  * 2. Save the transmitting data from the starting address of Socket n TX buffer.\n
617  * 3. After saving the transmitting data, update @ref Sn_TX_WR to the increased value as many as transmitting data size.
618  * If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs),
619  * then the carry bit is ignored and will automatically update with the lower 16bits value.\n
620  * 4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command
621  */
622  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__TX_WR = 0x0024
623 
624  /**
625  * @ingroup Socket_register_group
626  * @brief Received data size register(R)
627  * @details @ref Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer.
628  * @ref Sn_RX_RSR does not exceed the @ref Sn_RXBUF_SIZE and is calculated as the difference between
629  * �Socket n RX Write Pointer (@ref Sn_RX_WR)and �Socket n RX Read Pointer (@ref Sn_RX_RD)
630  */
631  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__RX_RSR = 0x0026
632 
633  /**
634  * @ingroup Socket_register_group
635  * @brief Read point of Receive memory(R/W)
636  * @details @ref Sn_RX_RD is initialized by OPEN command. Make sure to be read or updated as follows.\n
637  * 1. Read the starting save address of the received data.\n
638  * 2. Read data from the starting address of Socket n RX Buffer.\n
639  * 3. After reading the received data, Update @ref Sn_RX_RD to the increased value as many as the reading size.
640  * If the increment value exceeds the maximum value 0xFFFF, that is, is greater than 0x10000 and the carry bit occurs,
641  * update with the lower 16bits value ignored the carry bit.\n
642  * 4. Order RECV command is for notifying the updated @ref Sn_RX_RD to W5500.
643  */
644  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__RX_RD = 0x0028
645 
646  /**
647  * @ingroup Socket_register_group
648  * @brief Write point of Receive memory(R)
649  * @details @ref Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception.
650  * If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs),
651  * then the carry bit is ignored and will automatically update with the lower 16bits value.
652  */
653  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__RX_WR = 0x002A
654 
655  /**
656  * @ingroup Socket_register_group
657  * @brief socket interrupt mask register(R)
658  * @details @ref Sn_IMR masks the interrupt of Socket n.
659  * Each bit corresponds to each bit of @ref Sn_IR. When a Socket n Interrupt is occurred and the corresponding bit of @ref Sn_IMR is
660  * the corresponding bit of @ref Sn_IR becomes When both the corresponding bit of @ref Sn_IMR and @ref Sn_IR are and the n-th bit of @ref IR is
661  * Host is interrupted by asserted INTn PIN to low.
662  */
663  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__IMR = 0x002C
664 
665  /**
666  * @ingroup Socket_register_group
667  * @brief Fragment field value in IP header register(R/W)
668  * @details @ref Sn_FRAG configures the FRAG(Fragment field in IP header).
669  */
670  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__FRAG = 0x002D
671 
672  /**
673  * @ingroup Socket_register_group
674  * @brief Keep Alive Timer register(R/W)
675  * @details @ref Sn_KPALVTR configures the transmitting timer of �KEEP ALIVE(KA)packet of SOCKETn. It is valid only in TCP mode,
676  * and ignored in other modes. The time unit is 5s.
677  * KA packet is transmittable after @ref Sn_SR is changed to SOCK_ESTABLISHED and after the data is transmitted or received to/from a peer at least once.
678  * In case of '@ref Sn_KPALVTR > 0', W5500 automatically transmits KA packet after time-period for checking the TCP connection (Auto-keepalive-process).
679  * In case of '@ref Sn_KPALVTR = 0', Auto-keep-alive-process will not operate,
680  * and KA packet can be transmitted by SEND_KEEP command by the host (Manual-keep-alive-process).
681  * Manual-keep-alive-process is ignored in case of '@ref Sn_KPALVTR > 0'.
682  */
683  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__KPALVTR = 0x002F
684 
685  //#define Sn_TSR(N) 0x0030
686 }zrtos_vfs_module_w5500_socket_register_t;
687 
688 //----------------------------- W5500 Register values -----------------------------
689 
690 /* MODE register values */
691 typedef enum{
692  /**
693  * @brief Reset
694  * @details If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset.
695  */
696  ZRTOS_VFS_MODULE_W5500_REGISTER_MODE__RST = 0x80
697 
698  /**
699  * @brief Wake on LAN
700  * @details 0 : Disable WOL mode\n
701  * 1 : Enable WOL mode\n
702  * If WOL mode is enabled and the received magic packet over UDP has been normally processed, the Interrupt PIN (INTn) asserts to low.
703  * When using WOL mode, the UDP Socket should be opened with any source port number. (Refer to Socket n Mode Register (@ref Sn_MR) for opening Socket.)
704  * @note The magic packet over UDP supported by W5500 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and
705  * 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode.
706  */
707  ,ZRTOS_VFS_MODULE_W5500_REGISTER_MODE__WOL = 0x20
708 
709  /**
710  * @brief Ping block
711  * @details 0 : Disable Ping block\n
712  * 1 : Enable Ping block\n
713  * If the bit is it blocks the response to a ping request.
714  */
715  ,ZRTOS_VFS_MODULE_W5500_REGISTER_MODE__PB = 0x10
716 
717  /**
718  * @brief Enable PPPoE
719  * @details 0 : DisablePPPoE mode\n
720  * 1 : EnablePPPoE mode\n
721  * If you use ADSL, this bit should be
722  */
723  ,ZRTOS_VFS_MODULE_W5500_REGISTER_MODE__PPPOE = 0x08
724 
725  /**
726  * @brief Enable UDP_FORCE_ARP CHECHK
727  * @details 0 : Disable Force ARP mode\n
728  * 1 : Enable Force ARP mode\n
729  * In Force ARP mode, It forces on sending ARP Request whenever data is sent.
730  */
731  ,ZRTOS_VFS_MODULE_W5500_REGISTER_MODE__FARP = 0x02
732 }zrtos_vfs_module_w5500_register_mode_t;
733 
734 /* IR register values */
735 typedef enum{
736  /**
737  * @brief Check IP conflict.
738  * @details Bit is set as when own source IP address is same with the sender IP address in the received ARP request.
739  */
740  ZRTOS_VFS_MODULE_W5500_REGISTER_INTERRUPT__CONFLICT = 0x80
741 
742  /**
743  * @brief Get the destination unreachable message in UDP sending.
744  * @details When receiving the ICMP (Destination port unreachable) packet, this bit is set as
745  * When this bit is Destination Information such as IP address and Port number may be checked with the corresponding @ref UIPR & @ref UPORTR.
746  */
747  ,ZRTOS_VFS_MODULE_W5500_REGISTER_INTERRUPT__UNREACH = 0x40
748 
749  /**
750  * @brief Get the PPPoE close message.
751  * @details When PPPoE is disconnected during PPPoE mode, this bit is set.
752  */
753  ,ZRTOS_VFS_MODULE_W5500_REGISTER_INTERRUPT__PPPoE = 0x20
754 
755  /**
756  * @brief Get the magic packet interrupt.
757  * @details When WOL mode is enabled and receives the magic packet over UDP, this bit is set.
758  */
759  ,ZRTOS_VFS_MODULE_W5500_REGISTER_INTERRUPT__MP = 0x10
760 }zrtos_vfs_module_w5500_register_interrupt_t;
761 
762 /* PHYCFGR register value */
763 typedef enum{
764  ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__RST = ~(1<<7) //< For PHY reset, must operate AND mask.
765  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__OPMD = (1<<6) // Configre PHY with OPMDC value
766  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__OPMDC_ALLA = (7<<3)
767  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__OPMDC_PDOWN = (6<<3)
768  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__OPMDC_NA = (5<<3)
769  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__OPMDC_100FA = (4<<3)
770  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__OPMDC_100F = (3<<3)
771  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__OPMDC_100H = (2<<3)
772  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__OPMDC_10F = (1<<3)
773  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__OPMDC_10H = (0<<3)
774  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__DPX_FULL = (1<<2)
775  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__DPX_HALF = (0<<2)
776  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__SPD_100 = (1<<1)
777  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__SPD_10 = (0<<1)
778  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__LNK_ON = (1<<0)
779  ,ZRTOS_VFS_MODULE_W5500_REGISTER_PHY__LNK_OFF = (0<<0)
780 }zrtos_vfs_module_w5500_register_phy_config_t;
781 
782 /* IMR register values */
783 typedef enum{
784  /**
785  * @brief IP Conflict Interrupt Mask.
786  * @details 0: Disable IP Conflict Interrupt\n
787  * 1: Enable IP Conflict Interrupt
788  */
789  ZRTOS_VFS_MODULE_W5500_REGISTER_IMR__IR7 = 0x80
790 
791  /**
792  * @brief Destination unreachable Interrupt Mask.
793  * @details 0: Disable Destination unreachable Interrupt\n
794  * 1: Enable Destination unreachable Interrupt
795  */
796  ,ZRTOS_VFS_MODULE_W5500_REGISTER_IMR__IR6 = 0x40
797 
798  /**
799  * @brief PPPoE Close Interrupt Mask.
800  * @details 0: Disable PPPoE Close Interrupt\n
801  * 1: Enable PPPoE Close Interrupt
802  */
803  ,ZRTOS_VFS_MODULE_W5500_REGISTER_IMR__IR5 = 0x20
804 
805  /**
806  * @brief Magic Packet Interrupt Mask.
807  * @details 0: Disable Magic Packet Interrupt\n
808  * 1: Enable Magic Packet Interrupt
809  */
810  ,ZRTOS_VFS_MODULE_W5500_REGISTER_IMR__IR4 = 0x10
811 }zrtos_vfs_module_w5500_register_imr_t;
812 
813 /* Sn_MR Default values */
814 typedef enum{
815  /**
816  * @brief Support UDP Multicasting
817  * @details 0 : disable Multicasting\n
818  * 1 : enable Multicasting\n
819  * This bit is applied only during UDP mode(P[3:0] = 010.\n
820  * To use multicasting, @ref Sn_DIPR & @ref Sn_DPORT should be respectively configured with the multicast group IP address & port number
821  * before Socket n is opened by OPEN command of @ref Sn_CR.
822  */
823  ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__MULTI = 0x80
824 
825  /**
826  * @brief Broadcast block in UDP Multicasting.
827  * @details 0 : disable Broadcast Blocking\n
828  * 1 : enable Broadcast Blocking\n
829  * This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = 010.\m
830  * In addition, This bit does when MACRAW mode(P[3:0] = 100
831  */
832  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__BCASTB = 0x40
833 
834  /**
835  * @brief No Delayed Ack(TCP), Multicast flag
836  * @details 0 : Disable No Delayed ACK option\n
837  * 1 : Enable No Delayed ACK option\n
838  * This bit is applied only during TCP mode (P[3:0] = 001.\n
839  * When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.\n
840  * When this bit is It sends the ACK packet after waiting for the timeout time configured by @ref _RTR_.
841  */
842  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__ND = 0x20
843 
844  /**
845  * @brief Unicast Block in UDP Multicasting
846  * @details 0 : disable Unicast Blocking\n
847  * 1 : enable Unicast Blocking\n
848  * This bit blocks receiving the unicast packet during UDP mode(P[3:0] = 010 and MULTI =
849  */
850  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__UCASTB = 0x10
851 
852  /**
853  * @brief MAC LAYER RAW SOCK
854  * @details This configures the protocol mode of Socket n.
855  * @note MACRAW mode should be only used in Socket 0.
856  */
857  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__MACRAW = 0x04
858 
859  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__IPRAW = 0x03 /**< IP LAYER RAW SOCK */
860 
861  /**
862  * @brief UDP
863  * @details This configures the protocol mode of Socket n.
864  */
865  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__UDP = 0x02
866 
867  /**
868  * @brief TCP
869  * @details This configures the protocol mode of Socket n.
870  */
871  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__TCP = 0x01
872 
873  /**
874  * @brief Unused socket
875  * @details This configures the protocol mode of Socket n.
876  */
877  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__CLOSE = 0x00
878 
879  /* Sn_MR values used with Sn_MR_MACRAW */
880  /**
881  * @brief MAC filter enable in @ref Sn_MR_MACRAW mode
882  * @details 0 : disable MAC Filtering\n
883  * 1 : enable MAC Filtering\n
884  * This bit is applied only during MACRAW mode(P[3:0] = 100.\n
885  * When set as W5500 can only receive broadcasting packet or packet sent to itself.
886  * When this bit is W5500 can receive all packets on Ethernet.
887  * If user wants to implement Hybrid TCP/IP stack,
888  * it is recommended that this bit is set as for reducing host overhead to process the all received packets.
889  */
890  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__MFEN = ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__MULTI
891 
892  /**
893  * @brief Multicast Blocking in @ref Sn_MR_MACRAW mode
894  * @details 0 : using IGMP version 2\n
895  * 1 : using IGMP version 1\n
896  * This bit is applied only during UDP mode(P[3:0] = 010 and MULTI =
897  * It configures the version for IGMP messages (Join/Leave/Report).
898  */
899  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__MMB = ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__ND
900 
901  /**
902  * @brief IPv6 packet Blocking in @ref Sn_MR_MACRAW mode
903  * @details 0 : disable IPv6 Blocking\n
904  * 1 : enable IPv6 Blocking\n
905  * This bit is applied only during MACRAW mode (P[3:0] = 100. It blocks to receiving the IPv6 packet.
906  */
907  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__MIP6B = ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__UCASTB
908 
909  /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */
910  /**
911  * @brief IGMP version used in UDP mulitcasting
912  * @details 0 : disable Multicast Blocking\n
913  * 1 : enable Multicast Blocking\n
914  * This bit is applied only when MACRAW mode(P[3:0] = 100. It blocks to receive the packet with multicast MAC address.
915  */
916  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__MC = ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__ND
917 
918  /* Sn_MR alternate values */
919  /**
920  * @brief For Berkeley Socket API
921  */
922  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__STREAM = ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__TCP
923 
924  /**
925  * @brief For Berkeley Socket API
926  */
927  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__DGRAM = ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_MODE__UDP
928 }zrtos_vfs_module_w5500_socket_register_mode_t;
929 
930 /* Sn_CR values */
931 typedef enum{
932  /**
933  * @brief Initialize or open socket
934  * @details Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0).
935  * The table below shows the value of @ref Sn_SR corresponding to @ref Sn_MR.\n
936  * <table>
937  * <tr> <td>\b Sn_MR (P[3:0])</td> <td>\b Sn_SR</td> </tr>
938  * <tr> <td>Sn_MR_CLOSE (000)</td> <td></td> </tr>
939  * <tr> <td>Sn_MR_TCP (001)</td> <td>SOCK_INIT (0x13)</td> </tr>
940  * <tr> <td>Sn_MR_UDP (010)</td> <td>SOCK_UDP (0x22)</td> </tr>
941  * <tr> <td>S0_MR_MACRAW (100)</td> <td>SOCK_MACRAW (0x02)</td> </tr>
942  * </table>
943  */
944  ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_COMMAND__OPEN = 0x01
945 
946  /**
947  * @brief Wait connection request in TCP mode(Server mode)
948  * @details This is valid only in TCP mode (\ref Sn_MR(P3:P0) = \ref Sn_MR_TCP).
949  * In this mode, Socket n operates as a TCP serverand waits for connection-request (SYN packet) from any TCP client
950  * The @ref Sn_SR changes the state from \ref SOCK_INIT to \ref SOCKET_LISTEN.
951  * When a TCP clientconnection request is successfully established,
952  * the @ref Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the @ref Sn_IR(0) becomes
953  * But when a TCP clientconnection request is failed, @ref Sn_IR(3) becomes and the status of @ref Sn_SR changes to SOCK_CLOSED.
954  */
955  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_COMMAND__LISTEN = 0x02
956 
957  /**
958  * @brief Send connection request in TCP mode(Client mode)
959  * @details To connect, a connect-request (SYN packet) is sent to <b>TCP server</b>configured by @ref Sn_DIPR & Sn_DPORT(destination address & port).
960  * If the connect-request is successful, the @ref Sn_SR is changed to @ref SOCK_ESTABLISHED and the Sn_IR(0) becomes \n\n
961  * The connect-request fails in the following three cases.\n
962  * 1. When a @b ARPTO occurs (@ref Sn_IR[3] = ) because destination hardware address is not acquired through the ARP-process.\n
963  * 2. When a @b SYN/ACK packet is not received and @b TCPTO (Sn_IR(3) = )\n
964  * 3. When a @b RST packet is received instead of a @b SYN/ACK packet. In these cases, @ref Sn_SR is changed to @ref SOCK_CLOSED.
965  * @note This is valid only in TCP mode and operates when Socket n acts as <b>TCP client</b>
966  */
967  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_COMMAND__CONNECT = 0x04
968 
969  /**
970  * @brief Send closing request in TCP mode
971  * @details Regardless of <b>TCP server</b>or <b>TCP client</b> the DISCON command processes the disconnect-process (b>Active close</b>or <b>Passive close</b>.\n
972  * @par Active close
973  * it transmits disconnect-request(FIN packet) to the connected peer\n
974  * @par Passive close
975  * When FIN packet is received from peer, a FIN packet is replied back to the peer.\n
976  * @details When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), @ref Sn_SR is changed to @ref SOCK_CLOSED.\n
977  * Otherwise, TCPTO occurs (\ref Sn_IR(3)='1') and then @ref Sn_SR is changed to @ref SOCK_CLOSED.
978  * @note Valid only in TCP mode.
979  */
980  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_COMMAND__DISCON = 0x08
981 
982  /**
983  * @brief Close socket
984  * @details Sn_SR is changed to @ref SOCK_CLOSED.
985  */
986  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_COMMAND__CLOSE = 0x10
987 
988  /**
989  * @brief Update TX buffer pointer and send data
990  * @details SEND transmits all the data in the Socket n TX buffer.\n
991  * For more details, please refer to Socket n TX Free Size Register (@ref Sn_TX_FSR), Socket n,
992  * TX Write Pointer Register(@ref Sn_TX_WR), and Socket n TX Read Pointer Register(@ref Sn_TX_RD).
993  */
994  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_COMMAND__SEND = 0x20
995 
996  /**
997  * @brief Send data with MAC address, so without ARP process
998  * @details The basic operation is same as SEND.\n
999  * Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).\n
1000  * But SEND_MAC transmits data without the automatic ARP-process.\n
1001  * In this case, the destination hardware address is acquired from @ref Sn_DHAR configured by host, instead of APR-process.
1002  * @note Valid only in UDP mode.
1003  */
1004  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_COMMAND__SEND_MAC = 0x21
1005 
1006  /**
1007  * @brief Send keep alive message
1008  * @details It checks the connection status by sending 1byte keep-alive packet.\n
1009  * If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur.
1010  * @note Valid only in TCP mode.
1011  */
1012  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_COMMAND__SEND_KEEP = 0x22
1013 
1014  /**
1015  * @brief Update RX buffer pointer and receive data
1016  * @details RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (@ref Sn_RX_RD).\n
1017  * For more details, refer to Socket n RX Received Size Register (@ref Sn_RX_RSR), Socket n RX Write Pointer Register (@ref Sn_RX_WR),
1018  * and Socket n RX Read Pointer Register (@ref Sn_RX_RD).
1019  */
1020  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_COMMAND__RECV = 0x40
1021 }zrtos_vfs_module_w5500_socket_register_command_t;
1022 
1023 typedef enum{
1024  /* Sn_IR values */
1025  /**
1026  * @brief SEND_OK Interrupt
1027  * @details This is issued when SEND command is completed.
1028  */
1029  ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_INTERRUPT__SENDOK = 0x10
1030 
1031  /**
1032  * @brief TIMEOUT Interrupt
1033  * @details This is issued when ARPTO or TCPTO occurs.
1034  */
1035  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_INTERRUPT__TIMEOUT = 0x08
1036 
1037  /**
1038  * @brief RECV Interrupt
1039  * @details This is issued whenever data is received from a peer.
1040  */
1041  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_INTERRUPT__RECV = 0x04
1042 
1043  /**
1044  * @brief DISCON Interrupt
1045  * @details This is issued when FIN or FIN/ACK packet is received from a peer.
1046  */
1047  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_INTERRUPT__DISCON = 0x02
1048 
1049  /**
1050  * @brief CON Interrupt
1051  * @details This is issued one time when the connection with peer is successful and then @ref Sn_SR is changed to @ref SOCK_ESTABLISHED.
1052  */
1053  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_INTERRUPT__CON = 0x01
1054 }zrtos_vfs_module_w5500_socket_register_interrupt_t;
1055 
1056 /* Sn_SR values */
1057 typedef enum{
1058  /**
1059  * @brief Closed
1060  * @details This indicates that Socket n is released.\n
1061  * When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to @ref SOCK_CLOSED regardless of previous status.
1062  */
1063  ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__CLOSED = 0x00
1064 
1065  /**
1066  * @brief Initiate state
1067  * @details This indicates Socket n is opened with TCP mode.\n
1068  * It is changed to @ref SOCK_INIT when @ref Sn_MR(P[3:0]) = 001 and OPEN command is ordered.\n
1069  * After @ref SOCK_INIT, user can use LISTEN /CONNECT command.
1070  */
1071  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__INIT = 0x13
1072 
1073  /**
1074  * @brief Listen state
1075  * @details This indicates Socket n is operating as <b>TCP server</b>mode and waiting for connection-request (SYN packet) from a peer <b>TCP client</b>.\n
1076  * It will change to @ref SOCK_ESTALBLISHED when the connection-request is successfully accepted.\n
1077  * Otherwise it will change to @ref SOCK_CLOSED after TCPTO @ref Sn_IR(TIMEOUT) = '1') is occurred.
1078  */
1079  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__LISTEN = 0x14
1080 
1081  /**
1082  * @brief Connection state
1083  * @details This indicates Socket n sent the connect-request packet (SYN packet) to a peer.\n
1084  * It is temporarily shown when @ref Sn_SR is changed from @ref SOCK_INIT to @ref SOCK_ESTABLISHED by CONNECT command.\n
1085  * If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to @ref SOCK_ESTABLISHED.\n
1086  * Otherwise, it changes to @ref SOCK_CLOSED after TCPTO (@ref Sn_IR[TIMEOUT] = '1') is occurred.
1087  */
1088  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__SYNSENT = 0x15
1089 
1090  /**
1091  * @brief Connection state
1092  * @details It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.\n
1093  * If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to @ref SOCK_ESTABLISHED. \n
1094  * If not, it changes to @ref SOCK_CLOSED after timeout (@ref Sn_IR[TIMEOUT] = '1') is occurred.
1095  */
1096  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__SYNRECV = 0x16
1097 
1098  /**
1099  * @brief Success to connect
1100  * @details This indicates the status of the connection of Socket n.\n
1101  * It changes to @ref SOCK_ESTABLISHED when the <b>TCP SERVER</b>processed the SYN packet from the <b>TCP CLIENT</b>during @ref SOCK_LISTEN, or
1102  * when the CONNECT command is successful.\n
1103  * During @ref SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command.
1104  */
1105  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__ESTABLISHED = 0x17
1106 
1107  /**
1108  * @brief Closing state
1109  * @details These indicate Socket n is closing.\n
1110  * These are shown in disconnect-process such as active-close and passive-close.\n
1111  * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED.
1112  */
1113  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__FIN_WAIT = 0x18
1114 
1115  /**
1116  * @brief Closing state
1117  * @details These indicate Socket n is closing.\n
1118  * These are shown in disconnect-process such as active-close and passive-close.\n
1119  * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED.
1120  */
1121  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__CLOSING = 0x1A
1122 
1123  /**
1124  * @brief Closing state
1125  * @details These indicate Socket n is closing.\n
1126  * These are shown in disconnect-process such as active-close and passive-close.\n
1127  * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED.
1128  */
1129  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__TIME_WAIT = 0x1B
1130 
1131  /**
1132  * @brief Closing state
1133  * @details This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.\n
1134  * This is half-closing status, and data can be transferred.\n
1135  * For full-closing, DISCON command is used. But For just-closing, CLOSE command is used.
1136  */
1137  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__CLOSE_WAIT = 0x1C
1138 
1139  /**
1140  * @brief Closing state
1141  * @details This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.\n
1142  * It changes to @ref SOCK_CLOSED when Socket n received the response successfully, or when timeout(@ref Sn_IR[TIMEOUT] = '1') is occurred.
1143  */
1144  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__LAST_ACK = 0x1D
1145 
1146  /**
1147  * @brief UDP socket
1148  * @details This indicates Socket n is opened in UDP mode(@ref Sn_MR(P[3:0]) = '010').\n
1149  * It changes to SOCK_UDP when @ref Sn_MR(P[3:0]) = '010' and @ref Sn_CR_OPEN command is ordered.\n
1150  * Unlike TCP mode, data can be transfered without the connection-process.
1151  */
1152  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__UDP = 0x22
1153 
1154  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__IPRAW = 0x32 /**< IP raw mode socket */
1155 
1156  /**
1157  * @brief MAC raw mode socket
1158  * @details This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.\n
1159  * It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100and OPEN command is ordered.\n
1160  * Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process.
1161  */
1162  ,ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER_STATUS__MACRAW = 0x42
1163 
1164  //#define SOCK_PPPOE 0x5F
1165 }zrtos_vfs_module_w5500_socket_register_status_t;
1166 
1167 /* IP PROTOCOL */
1168 typedef enum{
1169  ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_IP = 0 //< Dummy for IP
1170  ,ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_ICMP = 1 //< Control message protocol
1171  ,ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_IGMP = 2 //< Internet group management protocol
1172  ,ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_GGP = 3 //< Gateway^2 (deprecated)
1173  ,ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_TCP = 6 //< TCP
1174  ,ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_PUP = 12 //< PUP
1175  ,ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_UDP = 17 //< UDP
1176  ,ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_IDP = 22 //< XNS idp
1177  ,ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_ND = 77 //< UNOFFICIAL net disk protocol
1178  ,ZRTOS_VFS_MODULE_W5500_IPPROTO__IPPROTO_RAW = 255 //< Raw IP packet
1179 }zrtos_vfs_module_w5500_ipproto_t;
1180 
1181 #if 0
1182 /**
1183  * @brief Enter a critical section
1184  *
1185  * @details It is provided to protect your shared code which are executed without distribution. \n \n
1186  *
1187  * In non-OS environment, It can be just implemented by disabling whole interrupt.\n
1188  * In OS environment, You can replace it to critical section api supported by OS.
1189  *
1190  * \sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
1191  * \sa WIZCHIP_CRITICAL_EXIT()
1192  */
1193 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
1194 
1195 #ifdef _exit
1196 #undef _exit
1197 #endif
1198 
1199 /**
1200  * @brief Exit a critical section
1201  *
1202  * @details It is provided to protect your shared code which are executed without distribution. \n\n
1203  *
1204  * In non-OS environment, It can be just implemented by disabling whole interrupt. \n
1205  * In OS environment, You can replace it to critical section api supported by OS.
1206  *
1207  * @sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
1208  * @sa WIZCHIP_CRITICAL_ENTER()
1209  */
1210 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
1211 
1212 
1213 ////////////////////////
1214 // Basic I/O Function //
1215 ////////////////////////
1216 
1217 /**
1218  * @ingroup Basic_IO_function
1219  * @brief It reads 1 byte value from a register.
1220  * @param AddrSel Register address
1221  * @return The value of register
1222  */
1223 uint8_t WIZCHIP_READ (uint32_t AddrSel);
1224 
1225 /**
1226  * @ingroup Basic_IO_function
1227  * @brief It writes 1 byte value to a register.
1228  * @param AddrSel Register address
1229  * @param wb Write data
1230  * @return void
1231  */
1232 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
1233 
1234 /**
1235  * @ingroup Basic_IO_function
1236  * @brief It reads sequence data from registers.
1237  * @param AddrSel Register address
1238  * @param pBuf Pointer buffer to read data
1239  * @param len Data length
1240  */
1241 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1242 
1243 /**
1244  * @ingroup Basic_IO_function
1245  * @brief It writes sequence data to registers.
1246  * @param AddrSel Register address
1247  * @param pBuf Pointer buffer to write data
1248  * @param len Data length
1249  */
1250 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1251 
1252 /////////////////////////////////
1253 // Common Register I/O function //
1254 /////////////////////////////////
1255 /**
1256  * @ingroup Common_register_access_function
1257  * @brief Set Mode Register
1258  * @param (uint8_t)mr The value to be set.
1259  * @sa getMR()
1260  */
1261 #define setMR(mr) \
1262  WIZCHIP_WRITE(MR,mr)
1263 
1264 
1265 /**
1266  * @ingroup Common_register_access_function
1267  * @brief Get Mode Register
1268  * @return uint8_t. The value of Mode register.
1269  * @sa setMR()
1270  */
1271 #define getMR() \
1272  WIZCHIP_READ(MR)
1273 
1274 /**
1275  * @ingroup Common_register_access_function
1276  * @brief Set gateway IP address
1277  * @param (uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes.
1278  * @sa getGAR()
1279  */
1280 #define setGAR(gar) \
1281  WIZCHIP_WRITE_BUF(GAR,gar,4)
1282 
1283 /**
1284  * @ingroup Common_register_access_function
1285  * @brief Get gateway IP address
1286  * @param (uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes.
1287  * @sa setGAR()
1288  */
1289 #define getGAR(gar) \
1290  WIZCHIP_READ_BUF(GAR,gar,4)
1291 
1292 /**
1293  * @ingroup Common_register_access_function
1294  * @brief Set subnet mask address
1295  * @param (uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes.
1296  * @sa getSUBR()
1297  */
1298 #define setSUBR(subr) \
1299  WIZCHIP_WRITE_BUF(SUBR, subr,4)
1300 
1301 
1302 /**
1303  * @ingroup Common_register_access_function
1304  * @brief Get subnet mask address
1305  * @param (uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes.
1306  * @sa setSUBR()
1307  */
1308 #define getSUBR(subr) \
1309  WIZCHIP_READ_BUF(SUBR, subr, 4)
1310 
1311 /**
1312  * @ingroup Common_register_access_function
1313  * @brief Set local MAC address
1314  * @param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes.
1315  * @sa getSHAR()
1316  */
1317 #define setSHAR(shar) \
1318  WIZCHIP_WRITE_BUF(SHAR, shar, 6)
1319 
1320 /**
1321  * @ingroup Common_register_access_function
1322  * @brief Get local MAC address
1323  * @param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes.
1324  * @sa setSHAR()
1325  */
1326 #define getSHAR(shar) \
1327  WIZCHIP_READ_BUF(SHAR, shar, 6)
1328 
1329 /**
1330  * @ingroup Common_register_access_function
1331  * @brief Set local IP address
1332  * @param (uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes.
1333  * @sa getSIPR()
1334  */
1335 #define setSIPR(sipr) \
1336  WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
1337 
1338 /**
1339  * @ingroup Common_register_access_function
1340  * @brief Get local IP address
1341  * @param (uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes.
1342  * @sa setSIPR()
1343  */
1344 #define getSIPR(sipr) \
1345  WIZCHIP_READ_BUF(SIPR, sipr, 4)
1346 
1347 /**
1348  * @ingroup Common_register_access_function
1349  * @brief Set INTLEVEL register
1350  * @param (uint16_t)intlevel Value to set @ref INTLEVEL register.
1351  * @sa getINTLEVEL()
1352  */
1353 #define setINTLEVEL(intlevel) {\
1354  WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
1355  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
1356  }
1357 
1358 
1359 /**
1360  * @ingroup Common_register_access_function
1361  * @brief Get INTLEVEL register
1362  * @return uint16_t. Value of @ref INTLEVEL register.
1363  * @sa setINTLEVEL()
1364  */
1365 //M20150401 : Type explict declaration
1366 /*
1367 #define getINTLEVEL() \
1368  ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
1369 */
1370 #define getINTLEVEL() \
1371  (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
1372 
1373 /**
1374  * @ingroup Common_register_access_function
1375  * @brief Set @ref IR register
1376  * @param (uint8_t)ir Value to set @ref IR register.
1377  * @sa getIR()
1378  */
1379 #define setIR(ir) \
1380  WIZCHIP_WRITE(IR, (ir & 0xF0))
1381 
1382 /**
1383  * @ingroup Common_register_access_function
1384  * @brief Get @ref IR register
1385  * @return uint8_t. Value of @ref IR register.
1386  * @sa setIR()
1387  */
1388 #define getIR() \
1389  (WIZCHIP_READ(IR) & 0xF0)
1390 /**
1391  * @ingroup Common_register_access_function
1392  * @brief Set @ref _IMR_ register
1393  * @param (uint8_t)imr Value to set @ref _IMR_ register.
1394  * @sa getIMR()
1395  */
1396 #define setIMR(imr) \
1397  WIZCHIP_WRITE(_IMR_, imr)
1398 
1399 /**
1400  * @ingroup Common_register_access_function
1401  * @brief Get @ref _IMR_ register
1402  * @return uint8_t. Value of @ref _IMR_ register.
1403  * @sa setIMR()
1404  */
1405 #define getIMR() \
1406  WIZCHIP_READ(_IMR_)
1407 
1408 /**
1409  * @ingroup Common_register_access_function
1410  * @brief Set @ref SIR register
1411  * @param (uint8_t)sir Value to set @ref SIR register.
1412  * @sa getSIR()
1413  */
1414 #define setSIR(sir) \
1415  WIZCHIP_WRITE(SIR, sir)
1416 
1417 /**
1418  * @ingroup Common_register_access_function
1419  * @brief Get @ref SIR register
1420  * @return uint8_t. Value of @ref SIR register.
1421  * @sa setSIR()
1422  */
1423 #define getSIR() \
1424  WIZCHIP_READ(SIR)
1425 /**
1426  * @ingroup Common_register_access_function
1427  * @brief Set @ref SIMR register
1428  * @param (uint8_t)simr Value to set @ref SIMR register.
1429  * @sa getSIMR()
1430  */
1431 #define setSIMR(simr) \
1432  WIZCHIP_WRITE(SIMR, simr)
1433 
1434 /**
1435  * @ingroup Common_register_access_function
1436  * @brief Get @ref SIMR register
1437  * @return uint8_t. Value of @ref SIMR register.
1438  * @sa setSIMR()
1439  */
1440 #define getSIMR() \
1441  WIZCHIP_READ(SIMR)
1442 
1443 /**
1444  * @ingroup Common_register_access_function
1445  * @brief Set @ref _RTR_ register
1446  * @param (uint16_t)rtr Value to set @ref _RTR_ register.
1447  * @sa getRTR()
1448  */
1449 #define setRTR(rtr) {\
1450  WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \
1451  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
1452  }
1453 
1454 /**
1455  * @ingroup Common_register_access_function
1456  * @brief Get @ref _RTR_ register
1457  * @return uint16_t. Value of @ref _RTR_ register.
1458  * @sa setRTR()
1459  */
1460 //M20150401 : Type explict declaration
1461 /*
1462 #define getRTR() \
1463  ((WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
1464 */
1465 #define getRTR() \
1466  (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
1467 
1468 
1469 /**
1470  * @ingroup Common_register_access_function
1471  * @brief Set @ref _RCR_ register
1472  * @param (uint8_t)rcr Value to set @ref _RCR_ register.
1473  * @sa getRCR()
1474  */
1475 #define setRCR(rcr) \
1476  WIZCHIP_WRITE(_RCR_, rcr)
1477 
1478 /**
1479  * @ingroup Common_register_access_function
1480  * @brief Get @ref _RCR_ register
1481  * @return uint8_t. Value of @ref _RCR_ register.
1482  * @sa setRCR()
1483  */
1484 #define getRCR() \
1485  WIZCHIP_READ(_RCR_)
1486 
1487 //================================================== test done ===========================================================
1488 
1489 /**
1490  * @ingroup Common_register_access_function
1491  * @brief Set @ref PTIMER register
1492  * @param (uint8_t)ptimer Value to set @ref PTIMER register.
1493  * @sa getPTIMER()
1494  */
1495 #define setPTIMER(ptimer) \
1496  WIZCHIP_WRITE(PTIMER, ptimer)
1497 
1498 /**
1499  * @ingroup Common_register_access_function
1500  * @brief Get @ref PTIMER register
1501  * @return uint8_t. Value of @ref PTIMER register.
1502  * @sa setPTIMER()
1503  */
1504 #define getPTIMER() \
1505  WIZCHIP_READ(PTIMER)
1506 
1507 /**
1508  * @ingroup Common_register_access_function
1509  * @brief Set @ref PMAGIC register
1510  * @param (uint8_t)pmagic Value to set @ref PMAGIC register.
1511  * @sa getPMAGIC()
1512  */
1513 #define setPMAGIC(pmagic) \
1514  WIZCHIP_WRITE(PMAGIC, pmagic)
1515 
1516 /**
1517  * @ingroup Common_register_access_function
1518  * @brief Get @ref PMAGIC register
1519  * @return uint8_t. Value of @ref PMAGIC register.
1520  * @sa setPMAGIC()
1521  */
1522 #define getPMAGIC() \
1523  WIZCHIP_READ(PMAGIC)
1524 
1525 /**
1526  * @ingroup Common_register_access_function
1527  * @brief Set @ref PHAR address
1528  * @param (uint8_t*)phar Pointer variable to set PPP destination MAC register address. It should be allocated 6 bytes.
1529  * @sa getPHAR()
1530  */
1531 #define setPHAR(phar) \
1532  WIZCHIP_WRITE_BUF(PHAR, phar, 6)
1533 
1534 /**
1535  * @ingroup Common_register_access_function
1536  * @brief Get @ref PHAR address
1537  * @param (uint8_t*)phar Pointer variable to PPP destination MAC register address. It should be allocated 6 bytes.
1538  * @sa setPHAR()
1539  */
1540 #define getPHAR(phar) \
1541  WIZCHIP_READ_BUF(PHAR, phar, 6)
1542 
1543 /**
1544  * @ingroup Common_register_access_function
1545  * @brief Set @ref PSID register
1546  * @param (uint16_t)psid Value to set @ref PSID register.
1547  * @sa getPSID()
1548  */
1549 #define setPSID(psid) {\
1550  WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \
1551  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \
1552  }
1553 
1554 /**
1555  * @ingroup Common_register_access_function
1556  * @brief Get @ref PSID register
1557  * @return uint16_t. Value of @ref PSID register.
1558  * @sa setPSID()
1559  */
1560 //uint16_t getPSID(void);
1561 //M20150401 : Type explict declaration
1562 /*
1563 #define getPSID() \
1564  ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
1565 */
1566 #define getPSID() \
1567  (((uint16_t)WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
1568 
1569 /**
1570  * @ingroup Common_register_access_function
1571  * @brief Set @ref PMRU register
1572  * @param (uint16_t)pmru Value to set @ref PMRU register.
1573  * @sa getPMRU()
1574  */
1575 #define setPMRU(pmru) { \
1576  WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \
1577  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \
1578  }
1579 
1580 /**
1581  * @ingroup Common_register_access_function
1582  * @brief Get @ref PMRU register
1583  * @return uint16_t. Value of @ref PMRU register.
1584  * @sa setPMRU()
1585  */
1586 //M20150401 : Type explict declaration
1587 /*
1588 #define getPMRU() \
1589  ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
1590 */
1591 #define getPMRU() \
1592  (((uint16_t)WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
1593 
1594 /**
1595  * @ingroup Common_register_access_function
1596  * @brief Get unreachable IP address
1597  * @param (uint8_t*)uipr Pointer variable to get unreachable IP address. It should be allocated 4 bytes.
1598  */
1599 //M20150401 : Size Error of UIPR (6 -> 4)
1600 /*
1601 #define getUIPR(uipr) \
1602  WIZCHIP_READ_BUF(UIPR,uipr,6)
1603 */
1604 #define getUIPR(uipr) \
1605  WIZCHIP_READ_BUF(UIPR,uipr,4)
1606 
1607 /**
1608  * @ingroup Common_register_access_function
1609  * @brief Get @ref UPORTR register
1610  * @return uint16_t. Value of @ref UPORTR register.
1611  */
1612 //M20150401 : Type explict declaration
1613 /*
1614 #define getUPORTR() \
1615  ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
1616 */
1617 #define getUPORTR() \
1618  (((uint16_t)WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
1619 
1620 /**
1621  * @ingroup Common_register_access_function
1622  * @brief Set @ref PHYCFGR register
1623  * @param (uint8_t)phycfgr Value to set @ref PHYCFGR register.
1624  * @sa getPHYCFGR()
1625  */
1626 #define setPHYCFGR(phycfgr) \
1627  WIZCHIP_WRITE(PHYCFGR, phycfgr)
1628 
1629 /**
1630  * @ingroup Common_register_access_function
1631  * @brief Get @ref PHYCFGR register
1632  * @return uint8_t. Value of @ref PHYCFGR register.
1633  * @sa setPHYCFGR()
1634  */
1635 #define getPHYCFGR() \
1636  WIZCHIP_READ(PHYCFGR)
1637 
1638 /**
1639  * @ingroup Common_register_access_function
1640  * @brief Get @ref VERSIONR register
1641  * @return uint8_t. Value of @ref VERSIONR register.
1642  */
1643 #define getVERSIONR() \
1644  WIZCHIP_READ(VERSIONR)
1645 
1646 /////////////////////////////////////
1647 
1648 ///////////////////////////////////
1649 // Socket N register I/O function //
1650 ///////////////////////////////////
1651 /**
1652  * @ingroup Socket_register_access_function
1653  * @brief Set @ref Sn_MR register
1654  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1655  * @param (uint8_t)mr Value to set @ref Sn_MR
1656  * @sa getSn_MR()
1657  */
1658 #define setSn_MR(sn, mr) \
1659  WIZCHIP_WRITE(Sn_MR(sn),mr)
1660 
1661 /**
1662  * @ingroup Socket_register_access_function
1663  * @brief Get @ref Sn_MR register
1664  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1665  * @return uint8_t. Value of @ref Sn_MR.
1666  * @sa setSn_MR()
1667  */
1668 #define getSn_MR(sn) \
1669  WIZCHIP_READ(Sn_MR(sn))
1670 
1671 /**
1672  * @ingroup Socket_register_access_function
1673  * @brief Set @ref Sn_CR register
1674  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1675  * @param (uint8_t)cr Value to set @ref Sn_CR
1676  * @sa getSn_CR()
1677  */
1678 #define setSn_CR(sn, cr) \
1679  WIZCHIP_WRITE(Sn_CR(sn), cr)
1680 
1681 /**
1682  * @ingroup Socket_register_access_function
1683  * @brief Get @ref Sn_CR register
1684  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1685  * @return uint8_t. Value of @ref Sn_CR.
1686  * @sa setSn_CR()
1687  */
1688 #define getSn_CR(sn) \
1689  WIZCHIP_READ(Sn_CR(sn))
1690 
1691 /**
1692  * @ingroup Socket_register_access_function
1693  * @brief Set @ref Sn_IR register
1694  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1695  * @param (uint8_t)ir Value to set @ref Sn_IR
1696  * @sa getSn_IR()
1697  */
1698 #define setSn_IR(sn, ir) \
1699  WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
1700 
1701 /**
1702  * @ingroup Socket_register_access_function
1703  * @brief Get @ref Sn_IR register
1704  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1705  * @return uint8_t. Value of @ref Sn_IR.
1706  * @sa setSn_IR()
1707  */
1708 #define getSn_IR(sn) \
1709  (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
1710 
1711 /**
1712  * @ingroup Socket_register_access_function
1713  * @brief Set @ref Sn_IMR register
1714  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1715  * @param (uint8_t)imr Value to set @ref Sn_IMR
1716  * @sa getSn_IMR()
1717  */
1718 #define setSn_IMR(sn, imr) \
1719  WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
1720 
1721 /**
1722  * @ingroup Socket_register_access_function
1723  * @brief Get @ref Sn_IMR register
1724  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1725  * @return uint8_t. Value of @ref Sn_IMR.
1726  * @sa setSn_IMR()
1727  */
1728 #define getSn_IMR(sn) \
1729  (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
1730 
1731 /**
1732  * @ingroup Socket_register_access_function
1733  * @brief Get @ref Sn_SR register
1734  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1735  * @return uint8_t. Value of @ref Sn_SR.
1736  */
1737 #define getSn_SR(sn) \
1738  WIZCHIP_READ(Sn_SR(sn))
1739 
1740 /**
1741  * @ingroup Socket_register_access_function
1742  * @brief Set @ref Sn_PORT register
1743  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1744  * @param (uint16_t)port Value to set @ref Sn_PORT.
1745  * @sa getSn_PORT()
1746  */
1747 #define setSn_PORT(sn, port) { \
1748  WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
1749  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
1750  }
1751 
1752 /**
1753  * @ingroup Socket_register_access_function
1754  * @brief Get @ref Sn_PORT register
1755  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1756  * @return uint16_t. Value of @ref Sn_PORT.
1757  * @sa setSn_PORT()
1758  */
1759 //M20150401 : Type explict declaration
1760 /*
1761 #define getSn_PORT(sn) \
1762  ((WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1763 */
1764 #define getSn_PORT(sn) \
1765  (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1766 
1767 /**
1768  * @ingroup Socket_register_access_function
1769  * @brief Set @ref Sn_DHAR register
1770  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1771  * @param (uint8_t*)dhar Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes.
1772  * @sa getSn_DHAR()
1773  */
1774 #define setSn_DHAR(sn, dhar) \
1775  WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
1776 
1777 /**
1778  * @ingroup Socket_register_access_function
1779  * @brief Get @ref Sn_MR register
1780  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1781  * @param (uint8_t*)dhar Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes.
1782  * @sa setSn_DHAR()
1783  */
1784 #define getSn_DHAR(sn, dhar) \
1785  WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
1786 
1787 /**
1788  * @ingroup Socket_register_access_function
1789  * @brief Set @ref Sn_DIPR register
1790  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1791  * @param (uint8_t*)dipr Pointer variable to set socket n destination IP address. It should be allocated 4 bytes.
1792  * @sa getSn_DIPR()
1793  */
1794 #define setSn_DIPR(sn, dipr) \
1795  WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
1796 
1797 /**
1798  * @ingroup Socket_register_access_function
1799  * @brief Get @ref Sn_DIPR register
1800  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1801  * @param (uint8_t*)dipr Pointer variable to get socket n destination IP address. It should be allocated 4 bytes.
1802  * @sa setSn_DIPR()
1803  */
1804 #define getSn_DIPR(sn, dipr) \
1805  WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
1806 
1807 /**
1808  * @ingroup Socket_register_access_function
1809  * @brief Set @ref Sn_DPORT register
1810  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1811  * @param (uint16_t)dport Value to set @ref Sn_DPORT
1812  * @sa getSn_DPORT()
1813  */
1814 #define setSn_DPORT(sn, dport) { \
1815  WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
1816  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
1817  }
1818 
1819 /**
1820  * @ingroup Socket_register_access_function
1821  * @brief Get @ref Sn_DPORT register
1822  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1823  * @return uint16_t. Value of @ref Sn_DPORT.
1824  * @sa setSn_DPORT()
1825  */
1826 //M20150401 : Type explict declaration
1827 /*
1828 #define getSn_DPORT(sn) \
1829  ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1830 */
1831 #define getSn_DPORT(sn) \
1832  (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1833 
1834 /**
1835  * @ingroup Socket_register_access_function
1836  * @brief Set @ref Sn_MSSR register
1837  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1838  * @param (uint16_t)mss Value to set @ref Sn_MSSR
1839  * @sa setSn_MSSR()
1840  */
1841 #define setSn_MSSR(sn, mss) { \
1842  WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
1843  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
1844  }
1845 
1846 /**
1847  * @ingroup Socket_register_access_function
1848  * @brief Get @ref Sn_MSSR register
1849  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1850  * @return uint16_t. Value of @ref Sn_MSSR.
1851  * @sa setSn_MSSR()
1852  */
1853 //M20150401 : Type explict declaration
1854 /*
1855 #define getSn_MSSR(sn) \
1856  ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1857 */
1858 #define getSn_MSSR(sn) \
1859  (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1860 
1861 /**
1862  * @ingroup Socket_register_access_function
1863  * @brief Set @ref Sn_TOS register
1864  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1865  * @param (uint8_t)tos Value to set @ref Sn_TOS
1866  * @sa getSn_TOS()
1867  */
1868 #define setSn_TOS(sn, tos) \
1869  WIZCHIP_WRITE(Sn_TOS(sn), tos)
1870 
1871 /**
1872  * @ingroup Socket_register_access_function
1873  * @brief Get @ref Sn_TOS register
1874  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1875  * @return uint8_t. Value of Sn_TOS.
1876  * @sa setSn_TOS()
1877  */
1878 #define getSn_TOS(sn) \
1879  WIZCHIP_READ(Sn_TOS(sn))
1880 
1881 /**
1882  * @ingroup Socket_register_access_function
1883  * @brief Set @ref Sn_TTL register
1884  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1885  * @param (uint8_t)ttl Value to set @ref Sn_TTL
1886  * @sa getSn_TTL()
1887  */
1888 #define setSn_TTL(sn, ttl) \
1889  WIZCHIP_WRITE(Sn_TTL(sn), ttl)
1890 
1891 
1892 /**
1893  * @ingroup Socket_register_access_function
1894  * @brief Get @ref Sn_TTL register
1895  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1896  * @return uint8_t. Value of @ref Sn_TTL.
1897  * @sa setSn_TTL()
1898  */
1899 #define getSn_TTL(sn) \
1900  WIZCHIP_READ(Sn_TTL(sn))
1901 
1902 
1903 /**
1904  * @ingroup Socket_register_access_function
1905  * @brief Set @ref Sn_RXBUF_SIZE register
1906  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1907  * @param (uint8_t)rxbufsize Value to set @ref Sn_RXBUF_SIZE
1908  * @sa getSn_RXBUF_SIZE()
1909  */
1910 #define setSn_RXBUF_SIZE(sn, rxbufsize) \
1911  WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
1912 
1913 
1914 /**
1915  * @ingroup Socket_register_access_function
1916  * @brief Get @ref Sn_RXBUF_SIZE register
1917  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1918  * @return uint8_t. Value of @ref Sn_RXBUF_SIZE.
1919  * @sa setSn_RXBUF_SIZE()
1920  */
1921 #define getSn_RXBUF_SIZE(sn) \
1922  WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
1923 
1924 /**
1925  * @ingroup Socket_register_access_function
1926  * @brief Set @ref Sn_TXBUF_SIZE register
1927  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1928  * @param (uint8_t)txbufsize Value to set @ref Sn_TXBUF_SIZE
1929  * @sa getSn_TXBUF_SIZE()
1930  */
1931 #define setSn_TXBUF_SIZE(sn, txbufsize) \
1932  WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
1933 
1934 /**
1935  * @ingroup Socket_register_access_function
1936  * @brief Get @ref Sn_TXBUF_SIZE register
1937  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1938  * @return uint8_t. Value of @ref Sn_TXBUF_SIZE.
1939  * @sa setSn_TXBUF_SIZE()
1940  */
1941 #define getSn_TXBUF_SIZE(sn) \
1942  WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
1943 
1944 /**
1945  * @ingroup Socket_register_access_function
1946  * @brief Get @ref Sn_TX_FSR register
1947  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1948  * @return uint16_t. Value of @ref Sn_TX_FSR.
1949  */
1950 uint16_t getSn_TX_FSR(uint8_t sn);
1951 
1952 /**
1953  * @ingroup Socket_register_access_function
1954  * @brief Get @ref Sn_TX_RD register
1955  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1956  * @return uint16_t. Value of @ref Sn_TX_RD.
1957  */
1958 //M20150401 : Type explict declaration
1959 /*
1960 #define getSn_TX_RD(sn) \
1961  ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1962 */
1963 #define getSn_TX_RD(sn) \
1964  (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1965 
1966 /**
1967  * @ingroup Socket_register_access_function
1968  * @brief Set @ref Sn_TX_WR register
1969  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1970  * @param (uint16_t)txwr Value to set @ref Sn_TX_WR
1971  * @sa GetSn_TX_WR()
1972  */
1973 #define setSn_TX_WR(sn, txwr) { \
1974  WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
1975  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
1976  }
1977 
1978 /**
1979  * @ingroup Socket_register_access_function
1980  * @brief Get @ref Sn_TX_WR register
1981  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1982  * @return uint16_t. Value of @ref Sn_TX_WR.
1983  * @sa setSn_TX_WR()
1984  */
1985 //M20150401 : Type explict declaration
1986 /*
1987 #define getSn_TX_WR(sn) \
1988  ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1989 */
1990 #define getSn_TX_WR(sn) \
1991  (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1992 
1993 
1994 /**
1995  * @ingroup Socket_register_access_function
1996  * @brief Get @ref Sn_RX_RSR register
1997  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
1998  * @return uint16_t. Value of @ref Sn_RX_RSR.
1999  */
2000 uint16_t getSn_RX_RSR(uint8_t sn);
2001 
2002 
2003 /**
2004  * @ingroup Socket_register_access_function
2005  * @brief Set @ref Sn_RX_RD register
2006  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2007  * @param (uint16_t)rxrd Value to set @ref Sn_RX_RD
2008  * @sa getSn_RX_RD()
2009  */
2010 #define setSn_RX_RD(sn, rxrd) { \
2011  WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
2012  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
2013  }
2014 
2015 /**
2016  * @ingroup Socket_register_access_function
2017  * @brief Get @ref Sn_RX_RD register
2018  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2019  * @return uint16_t. Value of @ref Sn_RX_RD.
2020  * @sa setSn_RX_RD()
2021  */
2022 //M20150401 : Type explict declaration
2023 /*
2024 #define getSn_RX_RD(sn) \
2025  ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
2026 */
2027 #define getSn_RX_RD(sn) \
2028  (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
2029 
2030 /**
2031  * @ingroup Socket_register_access_function
2032  * @brief Get @ref Sn_RX_WR register
2033  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2034  * @return uint16_t. Value of @ref Sn_RX_WR.
2035  */
2036 //M20150401 : Type explict declaration
2037 /*
2038 #define getSn_RX_WR(sn) \
2039  ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
2040 */
2041 #define getSn_RX_WR(sn) \
2042  (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
2043 
2044 /**
2045  * @ingroup Socket_register_access_function
2046  * @brief Set @ref Sn_FRAG register
2047  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2048  * @param (uint16_t)frag Value to set @ref Sn_FRAG
2049  * @sa getSn_FRAD()
2050  */
2051 #define setSn_FRAG(sn, frag) { \
2052  WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
2053  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
2054  }
2055 
2056 /**
2057  * @ingroup Socket_register_access_function
2058  * @brief Get @ref Sn_FRAG register
2059  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2060  * @return uint16_t. Value of @ref Sn_FRAG.
2061  * @sa setSn_FRAG()
2062  */
2063 //M20150401 : Type explict declaration
2064 /*
2065 #define getSn_FRAG(sn) \
2066  ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
2067 */
2068 #define getSn_FRAG(sn) \
2069  (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
2070 
2071 /**
2072  * @ingroup Socket_register_access_function
2073  * @brief Set @ref Sn_KPALVTR register
2074  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2075  * @param (uint8_t)kpalvt Value to set @ref Sn_KPALVTR
2076  * @sa getSn_KPALVTR()
2077  */
2078 #define setSn_KPALVTR(sn, kpalvt) \
2079  WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
2080 
2081 /**
2082  * @ingroup Socket_register_access_function
2083  * @brief Get @ref Sn_KPALVTR register
2084  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2085  * @return uint8_t. Value of @ref Sn_KPALVTR.
2086  * @sa setSn_KPALVTR()
2087  */
2088 #define getSn_KPALVTR(sn) \
2089  WIZCHIP_READ(Sn_KPALVTR(sn))
2090 
2091 //////////////////////////////////////
2092 
2093 /////////////////////////////////////
2094 // Sn_TXBUF & Sn_RXBUF IO function //
2095 /////////////////////////////////////
2096 /**
2097  * @brief Socket_register_access_function
2098  * @brief Gets the max buffer size of socket sn passed as parameter.
2099  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2100  * @return uint16_t. Value of Socket n RX max buffer size.
2101  */
2102 //M20150401 : Type explict declaration
2103 /*
2104 #define getSn_RxMAX(sn) \
2105  (getSn_RXBUF_SIZE(sn) << 10)
2106 */
2107 #define getSn_RxMAX(sn) \
2108  (((uint16_t)getSn_RXBUF_SIZE(sn)) << 10)
2109 
2110 /**
2111  * @brief Socket_register_access_function
2112  * @brief Gets the max buffer size of socket sn passed as parameters.
2113  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2114  * @return uint16_t. Value of Socket n TX max buffer size.
2115  */
2116 //M20150401 : Type explict declaration
2117 /*
2118 #define getSn_TxMAX(sn) \
2119  (getSn_TXBUF_SIZE(sn) << 10)
2120 */
2121 #define getSn_TxMAX(sn) \
2122  (((uint16_t)getSn_TXBUF_SIZE(sn)) << 10)
2123 
2124 /**
2125  * @ingroup Basic_IO_function
2126  * @brief It copies data to internal TX memory
2127  *
2128  * @details This function reads the Tx write pointer register and after that,
2129  * it copies the <i>wizdata(pointer buffer)</i> of the length of <i>len(variable)</i> bytes to internal TX memory
2130  * and updates the Tx write pointer register.
2131  * This function is being called by send() and sendto() function also.
2132  *
2133  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2134  * @param wizdata Pointer buffer to write data
2135  * @param len Data length
2136  * @sa wiz_recv_data()
2137  */
2138 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2139 
2140 /**
2141  * @ingroup Basic_IO_function
2142  * @brief It copies data to your buffer from internal RX memory
2143  *
2144  * @details This function read the Rx read pointer register and after that,
2145  * it copies the received data from internal RX memory
2146  * to <i>wizdata(pointer variable)</i> of the length of <i>len(variable)</i> bytes.
2147  * This function is being called by recv() also.
2148  *
2149  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2150  * @param wizdata Pointer buffer to read data
2151  * @param len Data length
2152  * @sa wiz_send_data()
2153  */
2154 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2155 
2156 /**
2157  * @ingroup Basic_IO_function
2158  * @brief It discard the received data in RX memory.
2159  * @details It discards the data of the length of <i>len(variable)</i> bytes in internal RX memory.
2160  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
2161  * @param len Data length
2162  */
2163 void wiz_recv_ignore(uint8_t sn, uint16_t len);
2164 
2165 #endif
2166 
2167 #ifdef __cplusplus
2168 }
2169 #endif
2170 #endif
ZRTOS_VFS_MODULE_W5500_REGISTER_IMR__IR7
IP Conflict Interrupt Mask.
Definition: lib/w5500.h:789
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ZRTOS_VFS_MODULE_W5500_REGISTER__MR
Mode Register address(R/W) MR is used for S/W reset, ping block mode, PPPoE mode and etc...
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Definition: lib/w5500.h:194
ZRTOS_VFS_MODULE_W5500_SOCKET_REGISTER__MR
socket Mode register(R/W)
Definition: lib/w5500.h:435
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zrtos_vfs_module_w5500_socket_register_interrupt_t
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Definition: lib/w5500.h:404
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zrtos_vfs_module_w5500_socket_register_status_t
Definition: lib/w5500.h:1057
uint8_t
static uint8_t
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zrtos_vfs_module_w5500_register_mode_t
zrtos_vfs_module_w5500_register_mode_t
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